CMOS-CCD Signal Processor
Description
The CXL1517N/1518N are CMOS-CCD signal
processors developed for CCD camera complementary
color filter array processing system.
CXL1517N
452.5-bit
2, 453.5-bit 1H CCD delay line
CXL1518N
300.5-bit
2, 301.5-bit 1H CCD delay line
Features
Single 5V power supply
Low power consumption (Typ.)
CXL1517N
120mW
CXL1518N
75mW
Built-in peripheral circuits
Built-in CDS (Correlated Double Sampling) circuit
Functions
Clock driver
Autobias circuit (Center and black)
Pedestal clamp circuit
CDS circuit
Overflow prevention circuit
Absolute Maximum Ratings (Ta = 25C)
Supply voltage
V
DD
6
V
Operating temperature
Topr
10 to +65
C
Storage temperature
Tstg
55 to +150
C
Allowable power dissipation
P
D
350
mW (SSOP package)
Recommended Operating Voltage Range (Ta = 25C)
Supply voltage
V
DD
4.6 to 5.25
V
1
E91778A78-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXL1517N/1518N
24 pin SSOP (Plastic)
Structure
CMOS-CCD
Item
Symbol
V
L
V
H
f
CL
f
CL
Min.
V
SS
0.7
V
DD
Typ.
7.16
4.77
Max.
0.3
V
DD
V
DD
Unit
V
V
MHz
MHz
Remarks
NTSC: 455f
H
CCIR: 454f
H
NTSC: 910f
H
/3
CCIR: 908f
H
/3
Clock voltage Low
Clock voltage High
Clock
frequency
CXL1517N
CXL1518N
2
CXL1517N/1518N
Block Diagram and Pin Configuration (Top View)
8
10
14
16
17
1
V
D
D
ABCN
V
D
D
A
B
O
V
F
V
D
D
V
G
G
IN-B
IN-A
ABBL
V
S
S
X
D
L
1
X
D
L
2
V
S
S
V
S
S
C
D
S
C
L
P
A.B.
BLACK
CDS OUTPUT
CIRCUIT
CLP
DL
CDS OUTPUT
CIRCUIT
CLP
CDS OUTPUT
CIRCUIT
CLP
CLP PULSE
GEN.
OVERFLOW
PREVENTION
CIRCUIT
POTENTIAL
CONTROL
CDS
TIMING GENERATOR
9
11
15
OUT-C
OUT-A
OUT-B
7
2
6
IN-C
3
18
PG. GEN.
PG. GEN.
PG. GEN.
PRECHARGE
DRAIN
DRIVER
20
A.B.
CENTER
A
(n bit)
DL
B
(n bit)
DL
C
(n + 1 bit)
5
19
21
22
23
V
S
S
4
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
V
SS
IN-B
ABBL
V
DD
IN-C
CLP
V
DD
OUT-C
V
GG
V
DD
XDL2
V
SS
V
SS
CDS
OUT-A
NC
XDL1
21
22
23
24
ABCN
ABOVF
IN-A
NC
OUT-B
NC
V
SS
3
CXL1517N/1518N
Pin Description
Pin No.
Symbol
I/O
Description
Comment
V
SS
V
SS
IN-B
ABBL
V
DD
IN-C
CLP
V
DD
OUT-C
V
GG
OUT-B
NC
NC
OUT-A
CDS
V
SS
V
SS
XDL2
XDL1
V
DD
ABCN
ABOVF
IN-A
NC
--
--
I
O
--
I
I
--
O
O
O
--
--
O
O
--
--
I
I
--
O
O
I
--
GND
Signal input B channel (Y)
Autobias DC output for Y signal
Power supply
Signal input C channel (Y)
Clamp pulse input
Power supply
Signal output C channel
Output circuit bias DC output
Signal output B channel
--
--
Signal output A channel
DC output for CDS
GND
GND
Clock pulse input 2
Clock pulse input 1
Power supply
Autobias DC output for C signal
Autobias DC output for overflow prevention circuit
Signal input A channel (C)
--
Analog
Black level bias
Analog
Black level bias
at no clamp
>
100k
>
100k
Output circuit
Output circuit
Timing
>
100k
>
100k
Timing
Center level bias
at no clamp
>
100k
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
4
CXL1517N/1518N
Electrical Characteristics
f
CL
= 7.16MHz (CXL1517N)
Ta = 25
C, V
DD
= 5.0V, V
SS
= 0V
f
CL
= 4.77MHz (CXL1518N)
Item
Autobias center level
Autobias black level
Overflow prevention circuit
Autobias level
CDS source level
Output circuit bias level
Current
supply
Insertion gain
Frequency
response
Linearity
The insertion gain difference
between channels
Linearity difference
between channels
Cross-talk between channels
ABCN
ABBL
ABOVF
CDS
V
GG
I
DD
IG
f
G
Lin.
G
L
BC
CRT
V
1
V
2
V
3
V
4
V
5
A
1
V
6
V
6
V
6
V
6
Symbol
Test
point
SW conditions
Bias
conditions
SW1
a
a
a
a
a
b
b
b
c
b
b
b
b
b
a
a
a
b
b
b
b
a
a
a
a
a
a
a
to
c
a
to
c
a
to
c
a
to
c
a
a
a
a
a
a
a
a
a
a
b
SW2
SW3
SW4
to 6
E1
Min.
4.2
3.9
2.6
1.2
0.3
--
--
4.5
1.5
1.8
0
0
0
0
4.6
4.3
3.0
2.3
0.8
24
15
3.5
0.4
0.8
5
5
1
1
4.8
4.5
3.3
3.5
3.0
35
25
--
--
--
12
12
5
3
V
V
V
V
V
mA
dB
dB
%
%
%
%
Typ.
Max.
Conditions
20 log
20 log
Note 1)
Note 2)
Note 3)
Note 4)
Ratings
Unit
CXL1517N
CXL1518N
CXL1517N
CXL1518N
Bch
Cch
Output amplitude (mVp-p)
Input amplitude (SIN 100kHz, 100mVp-p)
V
1
A
V
1
B, C
V
2
+ 0.25V
A
V
1
B, C
V
2
+ 0.25V
Output amplitude (SIN 1MHz, 100mVp-p)
Output amplitude (SIN 100kHz, 100mVp-p)
Standard values are different between CXL1517N and CXL1518N.
5
CXL1517N/1518N
Notes)
1) Linearity testing
For A channel, set input bias to ABCN 0.2V first, and then set it to ABCN and ABCN + 0.2V. Then input a
sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. For B channel and C
channel, set input bias to ABBL + 0.45V first, and then set it to ABBL + 0.25V and ABBL + 0.05V. Then
input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. The maximum
output amplitude for the respective A, B and C channels is taken as Sout max and the minimum output
amplitude as Sout min. The linearity of the respective channels is defined as:
Lin. =
200 [%]
2) Calculation of insertion gain difference
As the maximum insertion gain among A, B and C channels is taken as Gmax and the minimum as Gmin,
the insertion gain difference between channels
G as:
G =
|
1 10
(
)
|
100 [%]
3) Calculation of linearity difference
Define B channel linearity as L
B
and C channel linearily as L
C
we obtain the difference
L
BC
as:
L
BC
=
|
L
B
L
C
|
[%]
4) Cross-talk calculation
CRTa
: The cross-talk value of A channel when B and C channels are input
OUT
A
-
a
: The output value of A channel when A channel is input
SW3-a, SW4-a, SW5, 6-b
OUT
A
-
bc
: The output value of A channel when B and C channels are input
(Cross-talk component)
SW3-a, SW4-b, SW5, 6-a
CRTa =
100 [%]
Clock Waveform Timing
Sout max Sout min
Sout max + Sout min
Gmax Gmin
20
OUT
A
-
bc
OUT
A
-
a
10ns
10%
50%
90%
XDL1
(52.5)
87.5ns
(140)
210ns
10%
50%
90%
10%
50%
90%
10%
50%
90%
XDL2
The value in brackets is for CXL1517N.
(52.5)
87.5ns
10ns
17.5ns
10ns
10ns
6
CXL1517N/1518N
10k 10k
10k
a
a
a
b
b
b
SW4
SW5
SW6
No signal (GND)
100kHz, 100mVp-p sine wave
1MHz, 100mVp-p sine wave
a
b
c
SW1
E1
V4
V5
V2
A1
V1
V
DD
3.3k
1
1
L.P.F
V6
b
a
c
SW3
1
16V
a
b
V
DD
1
16V
1
16V
1
16V
XDL
1
SW2
V3
1
16V
XDL
2
3.3k
3.3k
V
DD
V
DD
2
3
4
5
6
9
10
11
12
1
8
7
13
14
15
16
18
19
20
17
21
22
23
24
(NC)
(NC)
(NC)
V
DD
3.3k
3.3k
3.3k
1
16V
1
16V
1
16V
1
16V
XDL
1
1
16V
XDL
2
V
DD
V
DD
Output A
Output B
Output C
0.1
16V
100p
4.7
16V
V
DD
Input A
4.7
16V
100p
CLP
input
V
DD
Input
C
V
DD
4.7
16V
100p
0.1
16V
Input
B
11
12
13
14
15
16
18
19
20
17
3
4
5
6
10
1
8
9
7
2
0.1
16V
21
22
23
24
(NC)
(NC)
(NC)
Electrical Characteristics Test Circuit
Application Circuit
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
7
CXL1517N/1518N
Package Outline
Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
SSOP-24P-L01
SSOP024-P-0056
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER/PALLADIUM
42/COPPER ALLOY
PACKAGE STRUCTURE
PLATING
0.1g
24PIN SSOP(PLASTIC)
5
.
6
0
.
1
24
7.8 0.1
13
0.65
12
1
0.22 0.05
+ 0.1
0.15 0.02
+ 0.05
7
.
6
0
.
2
0.1
1.25 0.1
+ 0.2
A
0.1 0.1
0 to 10
0
.
5
0
.
2
DETAIL A
NOTE: Dimensions "
" does not include mold protrusion.
0.13 M
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